From Stanford CSD History

The S-1 project built a family of multiprocessor supercomputers. The project was envisioned by Lowell Wood at the Lawrence Livermore National Lab in 1975 and staffed for the first three years by two Stanford University Computer Science graduate students, Tom McWilliams and Curt Widdoes.

That two graduate students could design and almost completely build a supercomputer by themselves is an amazing feat, comparable to the design and building of the CDC 6600 by Seymour Cray and a small staff a dozen years earlier. However, McWilliams and Widdoes are even better known for the major advances in CAD tools for logic design that they developed as part of the early days of the project and for the startup company they founded, Valid Logic Systems. In this respect the S-1 project was similar to the Super Foonly project.

The project was supported by the US Navy and ramped up in 1978 with the addition of more students, including Mike Farmwald and Jeff Rubin, and again in 1979. Dr. Carl Haussman provided the day-to-day oversight as the project team grew in size.

Five generations of S-1 processors were planned, and two MSI/ECL generations were built. The project independently invented two-bit branch prediction, directory-based cache coherency, and multiprocessor synchronization using load linked and store conditional. The project also influenced the development of programming languages and compilers including Common LISP and gcc.

Contents 1 Timeline 1.1 1975 1.2 1976 1.3 1977 1.4 1978 1.5 1979 1.6 1980 1.7 1981 1.8 1982 1.9 1983 1.10 1984 1.11 1985 1.12 1986 1.13 1987 1.14 1988 2 Current Location of Hardware

Timeline

1975

Dr. Lowell Wood, a physicist at Lawrence Livermore National Laboratories and protégé of Edward Teller, led the special studies group at LLNL, which was called the O-Group. The O-Group members had many interests, but their work mainly revolved around ideas for a national missile defense. Wood was also an interviewer for the Hertz Foundation, which awarded prestigious scholarships to graduate students interested in the applied sciences. From this position, Wood could occasionally recruit top students to work at the lab.

Two Hertz Foundation scholarship recipients, Tom McWilliams and Curt Widdoes, enrolled in the Ph.D. program in computer science at Stanford in 1975 and came to work with Wood at LLNL. Wood challenged them to design and build a supercomputer. In fact, Wood envisioned a family of multiprocessor supercomputers, with each having nodes with compute power similar to contemporary commercial supercomputers. The plan was to build five generations of processors with the same general architecture and to develop computer-aided logic design tools that would ease the task of re-implementing the processors in each new logic technology family. The fifth generation was planned to use wafer-scale integration (WSI).

In the fall of 1975 McWilliams and Widdoes developed the instruction set and multiprocessor structure.

1976

1. In the Spring McWilliams and Widdoes used Stanford University Design System (SUDS) on the Stanford Artificial Intelligence Laboratory (SAIL) PDP-10 system to start drawing logic diagrams and developed the SCALD language to describe the design hierarchically.
2. In the Summer the wire lister was determined to be too demanding for a summer research associate to complete.
3. In the Fall McWilliams and Widdoes began implementation of SCALD I on the IBM System/370 model 168 at the Stanford Linear Accelerator Center.

1977

1. In the Spring the bulk of SCALD I was complete.
2. Summer saw the completion of the physical design subsystem, including simulation of signal waveforms.
3. By Fall the final S-1 Mark I wire list was ready.

1978

In the Spring additional personnel join the project, including Mike Farmwald and Jeff Rubin, for debugging Mark I and for the operating system.

1. In Summer the Mark I ran its first significant program and a single-user operating system. SCALD papers were presented at DAC.
   1. Each node was to have the processing power of a CDC 7600, though benchmarks indicated the completed processor was 1/3 the power of a 7600 or about the power of an IBM System/370 model 168.
   2. One node was built.
   3. 10 million instructions per second, 5300 chips, ECL-10K implementation (10 MHz).
   4. Originally planned (in around 1976) to have a 4,096-word instruction cache, a 4069-word data cache, both four-way set-associative with 4-word line size.
   5. No segmentation.
   6. The design required two man-years of effort using the specially-developed CAD tools; there were 211 high-level diagrams and 144 low-level diagrams.
   7. There were 12 boards, 5300 integrated circuits and three "pages" of logic; the pages unfold to allow access to wiring.
2. In the Fall work began on the Mark II and on SCALD II.

1979

1980

1981

1982

1983

1984

1985

1986

1987

1988

Current Location of Hardware

Historical reference material for the S-1 project is at Clemson University and at Stanford.