S-1 project
From Stanford CSD History
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| Two Hertz Foundation scholarship recipients, Tom McWilliams and Curt Widdoes, enrolled in the Ph.D. program in computer science at Stanford in 1975 and came to work with Wood at LLNL. Wood challenged them to design and build a supercomputer. In fact, Wood envisioned a family of multiprocessor supercomputers, with each having nodes with compute power similar to contemporary commercial supercomputers. The plan was to build five generations of processors with the same general architecture and to develop computer-aided logic design tools that would ease the task of re-implementing the processors in each new logic technology family. The fifth generation was planned to use wafer-scale integration (WSI). | Two Hertz Foundation scholarship recipients, Tom McWilliams and Curt Widdoes, enrolled in the Ph.D. program in computer science at Stanford in 1975 and came to work with Wood at LLNL. Wood challenged them to design and build a supercomputer. In fact, Wood envisioned a family of multiprocessor supercomputers, with each having nodes with compute power similar to contemporary commercial supercomputers. The plan was to build five generations of processors with the same general architecture and to develop computer-aided logic design tools that would ease the task of re-implementing the processors in each new logic technology family. The fifth generation was planned to use wafer-scale integration (WSI). | ||
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| + | In the fall of 1975 McWilliams and Widdoes developed the instruction set and multiprocessor structure. | ||
| == 1976 == | == 1976 == | ||
Revision as of 14:34, 19 October 2009
The S-1 project built a family of multiprocessor supercomputers. The project was envisioned by Lowell Wood at the Lawrence Livermore National Lab in 1975 and staffed for the first three years by two Stanford University Computer Science graduate students, Tom McWilliams and Curt Widdoes.
That two graduate students could design and almost completely build a supercomputer by themselves is an amazing feat, comparable to the design and building of the CDC 6600 by Seymour Cray and a small staff a dozen years earlier. However, McWilliams and Widdoes are even better known for the major advances in CAD tools for logic design that they developed as part of the early days of the project and for the startup company they founded, Valid Logic Systems. In this respect the S-1 project was similar to the Super Foonly project.
The project was supported by the US Navy and ramped up in 1978 with the addition of more students, including Mike Farmwald and Jeff Rubin, and again in 1979. Dr. Carl Haussman provided the day-to-day oversight as the project team grew in size.
Five generations of S-1 processors were planned, and two MSI/ECL generations were built. The project independently invented two-bit branch prediction, directory-based cache coherency, and multiprocessor synchronization using load linked and store conditional. The project also influenced the development of programming languages and compilers including Common LISP and gcc.
Contents |
Timeline
1975
Dr. Lowell Wood, a physicist at Lawrence Livermore National Laboratories and protégé of Edward Teller, led the special studies group at LLNL, which was called the O-Group. The O-Group members had many interests, but their work mainly revolved around ideas for a national missile defense. Wood was also an interviewer for the Hertz Foundation, which awarded prestigious scholarships to graduate students interested in the applied sciences. From this position, Wood could occasionally recruit top students to work at the lab.
Two Hertz Foundation scholarship recipients, Tom McWilliams and Curt Widdoes, enrolled in the Ph.D. program in computer science at Stanford in 1975 and came to work with Wood at LLNL. Wood challenged them to design and build a supercomputer. In fact, Wood envisioned a family of multiprocessor supercomputers, with each having nodes with compute power similar to contemporary commercial supercomputers. The plan was to build five generations of processors with the same general architecture and to develop computer-aided logic design tools that would ease the task of re-implementing the processors in each new logic technology family. The fifth generation was planned to use wafer-scale integration (WSI).
In the fall of 1975 McWilliams and Widdoes developed the instruction set and multiprocessor structure.
1976
1977
1978
Completion of the Mark I:
- Each node was to have the processing power of a CDC 7600, though benchmarks indicated the completed processor was 1/3 the power of a 7600 or about the power of an IBM System/370 model 168.
- One node was built.
- 10 million instructions per second, 5300 chips, ECL-10K implementation (10 MHz).
- Originally planned (in around 1976) to have a 4,096-word instruction cache, a 4069-word data cache, both four-way set-associative with 4-word line size.
- No segmentation.
- The design required two man-years of effort using the specially-developed CAD tools; there were 211 high-level diagrams and 144 low-level diagrams.
- There were 12 boards, 5300 integrated circuits, three "pages" of logic; the pages unfold to allow access to wiring.
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
Current Location of Hardware
Historical reference material for the S-1 project is at Clemson University and at Stanford.
