S-1 project

From Stanford CSD History

(Difference between revisions)

Revision as of 12:17, 20 October 2009

The S-1 project built a family of multiprocessor supercomputers. The project was envisioned by Dr. Lowell Wood at the Lawrence Livermore National Lab in 1975 and staffed for the first three years by two Stanford University Computer Science graduate students, Tom McWilliams and Curt Widdoes.

That two graduate students could design and almost completely build a supercomputer by themselves is an amazing feat, comparable to the design and building of the CDC 6600 by Seymour Cray and a small staff a dozen years earlier. However, McWilliams and Widdoes are even better known for the major advances in CAD tools for logic design that they developed as part of the early days of the project and for the startup company they founded, Valid Logic Systems. In this respect the S-1 project was similar to the Super Foonly project.

“What we did was the first practical use of structured design for designing a real computer—not a toy research project in a university, but a large computer that really worked.” — Curt Widdoes

The project ramped up in 1978 with the addition of more students, including Mike Farmwald and Jeff Rubin, and again in 1979. Dr. Carl Haussman provided the day-to-day oversight as the project team grew in size.

Five generations of S-1 processors were planned, and two MSI/ECL generations were built. The project independently invented two-bit branch prediction, directory-based cache coherency, and multiprocessor synchronization using load linked and store conditional. The project also influenced the development of programming languages and compilers including Common LISP and gcc.

Support for the S-1 project came initially from the Hertz grants, and later from the U.S. Navy, through the efforts of Dr. Lowell Wood and Dr. Edward Teller.

1 Timeline
- 1.1 1975
- 1.2 1976
- 1.3 1977
- 1.4 1978
- 1.5 1979
- 1.6 1980
- 1.7 1981
- 1.8 1982
- 1.9 1983
- 1.10 1984
- 1.11 1985
- 1.12 1986
- 1.13 1987
- 1.14 1988
2 Current Location of Hardware

Timeline

1975

Dr. Lowell Wood, a physicist at Lawrence Livermore National Laboratories (LLNL) and protégé of Edward Teller, led the special studies group at LLNL, which was called the O-Group. The O-Group members had many interests, but their work mainly revolved around ideas for a national missile defense. Wood was also an interviewer for the Hertz Foundation, which awarded prestigious scholarships to graduate students interested in the applied sciences. From this position, Wood could occasionally recruit top students to work at the lab.

In the ummer of 1975, two Hertz Foundation scholarship recipients, Tom McWilliams and Curt Widdoes, enrolled in the Ph.D. program in computer science at Stanford and came to work with Dr. Wood at LLNL. Wood challenged them to design and build a supercomputer. In fact, Wood envisioned a family of multiprocessor supercomputers, with each having nodes with compute power similar to contemporary commercial supercomputers. The plan was to build five generations of processors with the same general architecture and to develop computer-aided logic design tools that would ease the task of re-implementing the processors in each new logic technology family. The fifth generation was planned to use wafer-scale integration (WSI).

In the fall of 1975 McWilliams and Widdoes developed the instruction set and multiprocessor structure. The computer was to have a 36-bit word length. The 30-bit address counted 9-bit quarterwords, and instructions were 36 bits in length.

1976

In the spring of 1976 McWilliams and Widdoes used Stanford University Drawing System (SUDS) on the Stanford Artificial Intelligence Laboratory (SAIL) PDP-10 system to start drawing logic diagrams and developed the Structured Computer-Aided Logic Design (SCALD) language to describe the design hierarchically. SUDS was used as the base for SCALD. Although SUDS was written in PDP-10 assembly language, the other SCALD software was written in Pascal, so it could be run both on the SAIL PDP-10 and on the IBM System/370 model 168 at SLAC.
In the Summer the wire lister was determined to be too demanding for a summer research associate to complete.
In the Fall McWilliams and Widdoes began implementation of SCALD I on the IBM System/370 model 168 at the Stanford Linear Accelerator Center. The purpose of the SCALD Design System was to automate the conversion from a graphical, heirarchial block diagram to the low-level instructions for the wire-wrap machine[1]. The development debug cycle started with borrowed SUDS time on the PDP-10 at SAIL in the morning. When funded users arrived to use the PDP-10, the data was moved by magnetic tape to the IBM System/370 model 168 at SLAC for back-end processing. Those results were marked up by hand for editing the next morning on SUDS[2]. Time on the SLAC computer was also borrowed.

1977

In the Spring the bulk of SCALD I was complete.
Summer saw the completion of the physical design subsystem, including simulation of signal waveforms.
By Fall the final S-1 Mark I wire list was ready.

1978

In the Spring additional personnel join the project, including Mike Farmwald and Jeff Rubin, for debugging Mark I and for the operating system.

In Summer the Mark I ran its first significant program and a single-user operating system. SCALD papers were presented at the 15^th Annual Design Automation Conference.
1. Each node was to have the processing power of a CDC 7600, though benchmarks indicated the completed processor was 1/3 the power of a 7600 or about the power of an IBM System/370 model 168.
2. One node was built.
3. 10 million instructions per second, 5300 chips, ECL-10K implementation (10 MHz).
4. Originally planned (in around 1976) to have a 4,096-word instruction cache, a 4069-word data cache, both four-way set-associative with 4-word line size.
5. No segmentation.
6. The design required two man-years of effort using the specially-developed CAD tools; there were 211 high-level diagrams and 144 low-level diagrams.
7. There were 12 boards, each about 18 by 24 inches, with 5300 integrated circuits involving about 80,000 gates organized into three "pages" of logic; the pages unfold to allow access to wiring.
In the Fall work began on the Mark II and on SCALD II. Instead of depending on borrowed time at SAIL and SLAC, the group could now use the S-1 Mark I as its support computer.

1979

1980

1981

1982

1983

1984

1985

1986

1987

1988

Current Location of Hardware

Historical reference material for the S-1 project is at Clemson University and at Stanford. See also the S-1 Architecture Manual.

Retrieved from "http://www-forum.stanford.edu/wiki/index.php/S-1_project"