About The Forum
Calendar 2009 Poster Sessions : Energy-Efficient Processor Design
Abstract:
Power consumption has become a primary constraint in the design of microprocessors: power dissipation limits the achievable performance in high-performance processors and reduces battery life in low-power embedded devices. The challenge facing processor designers today, therefore, is to build energy-efficient designs that maximize performance in a given power budget. In this work, we present a systematic framework for optimizing a processor architecture for energy-efficiency. The processor design space consists of many design parameters and knobs. Each of these parameters can be used to increase performance, but comes at an energy cost. In our optimization framework, we use architectural and circuit models to find the optimal set of design parameters for efficient operation. As a case study, we apply this methodology to explore the power-performance tradeoffs in various different processor designs, and we show how the framework can be used to determine the optimal s et of design parameters when optimizing a processor system for energy-efficiency.
Bio:
Omid Azizi is a PhD candidate at Stanford, working under the supervision of Professor Mark Horowitz. His current research focus is on the design and optimization of processor architectures for energy-efficiency, and he is also a member the Chip Generator project. Omid has been at Stanford since September 2004, receiving his Master's degree in 2006. Outside Stanford, Omid has spent time at Intel's Microarchitecture Research Lab, and at Altera, as part of the physical synthesis group. Prior to coming to Stanford, Omid studied at the Unversity of Toronto, receiving his Bachelor's degree in Computer Engineering in 2004.
Power consumption has become a primary constraint in the design of microprocessors: power dissipation limits the achievable performance in high-performance processors and reduces battery life in low-power embedded devices. The challenge facing processor designers today, therefore, is to build energy-efficient designs that maximize performance in a given power budget. In this work, we present a systematic framework for optimizing a processor architecture for energy-efficiency. The processor design space consists of many design parameters and knobs. Each of these parameters can be used to increase performance, but comes at an energy cost. In our optimization framework, we use architectural and circuit models to find the optimal set of design parameters for efficient operation. As a case study, we apply this methodology to explore the power-performance tradeoffs in various different processor designs, and we show how the framework can be used to determine the optimal s et of design parameters when optimizing a processor system for energy-efficiency.
Bio:
Omid Azizi is a PhD candidate at Stanford, working under the supervision of Professor Mark Horowitz. His current research focus is on the design and optimization of processor architectures for energy-efficiency, and he is also a member the Chip Generator project. Omid has been at Stanford since September 2004, receiving his Master's degree in 2006. Outside Stanford, Omid has spent time at Intel's Microarchitecture Research Lab, and at Altera, as part of the physical synthesis group. Prior to coming to Stanford, Omid studied at the Unversity of Toronto, receiving his Bachelor's degree in Computer Engineering in 2004.