About The Forum
Calendar 2017 Poster Sessions : QED Effective Post-Silicon Validation and Debug
Abstract:
With the rapidly growing complexity of integrated circuits (ICs), critical design flaws (bugs) frequently escape pre-silicon verification. As a result, there is an increasing dependence on post-silicon validation of manufactured ICs in actual system environments to detect and fix these bugs. Existing post-silicon validation and debug techniques are mostly ad hoc and often involve manual steps. Such ad hoc approaches cannot scale with increasing IC complexity. Our Quick Error Detection (QED) technique systematically creates families of post-silicon validation tests that quickly detect bugs inside processor cores and uncore components of multi-core System on Chips (SoCs). Such quick detection is essential because long error detection latency, the time elapsed between the occurrence of an error due to a bug and an observable failure, is the most significant challenge limiting the effectiveness of traditional post-silicon validation techniques.
Symbolic Quick Error Detection (Symbolic QED) extends the methods developed in QED to provide a structured procedure for post-silicon validation and debug. This approach applies the error detecting QED transformations to formal analysis and uses bounded model checking to generate minimal-length bug activation traces that detect and localize any logic bugs in the design. Recent work has also focus on extending these techniques for electrical bug localization. Our results show that Symbolic QED: (i) is fully automatic, unlike manual techniques in use today that can be extremely time-consuming and expensive; (ii) requires only a few hours in contrast to current approaches that might take days (or even months) or formal techniques that often take days or fail completely for large designs; (iii) generates counter-examples (for activating and detecting logic bugs) that are up to 6 orders of magnitude shorter than those produced by traditional techniques.
Bio:
Eshan Singh received an ScB in Electrical Engineering, along with an AB in Economics, from Brown University in 2009. After completing an MS in Electrical Engineering from Stanford in 2011, Eshan spent three years at Intel as a Component Design Engineer. Eshan returned to Stanford in 2014 and is currently a PhD candidate with an interest in VLSI design, 3-D integrated circuits, computer architecture and validation and debug. His current research focuses on addressing challenges in post-silicon validation and debug, specifically aiming to improve bug localization and reduce debug time.
With the rapidly growing complexity of integrated circuits (ICs), critical design flaws (bugs) frequently escape pre-silicon verification. As a result, there is an increasing dependence on post-silicon validation of manufactured ICs in actual system environments to detect and fix these bugs. Existing post-silicon validation and debug techniques are mostly ad hoc and often involve manual steps. Such ad hoc approaches cannot scale with increasing IC complexity. Our Quick Error Detection (QED) technique systematically creates families of post-silicon validation tests that quickly detect bugs inside processor cores and uncore components of multi-core System on Chips (SoCs). Such quick detection is essential because long error detection latency, the time elapsed between the occurrence of an error due to a bug and an observable failure, is the most significant challenge limiting the effectiveness of traditional post-silicon validation techniques.
Symbolic Quick Error Detection (Symbolic QED) extends the methods developed in QED to provide a structured procedure for post-silicon validation and debug. This approach applies the error detecting QED transformations to formal analysis and uses bounded model checking to generate minimal-length bug activation traces that detect and localize any logic bugs in the design. Recent work has also focus on extending these techniques for electrical bug localization. Our results show that Symbolic QED: (i) is fully automatic, unlike manual techniques in use today that can be extremely time-consuming and expensive; (ii) requires only a few hours in contrast to current approaches that might take days (or even months) or formal techniques that often take days or fail completely for large designs; (iii) generates counter-examples (for activating and detecting logic bugs) that are up to 6 orders of magnitude shorter than those produced by traditional techniques.
Bio:
Eshan Singh received an ScB in Electrical Engineering, along with an AB in Economics, from Brown University in 2009. After completing an MS in Electrical Engineering from Stanford in 2011, Eshan spent three years at Intel as a Component Design Engineer. Eshan returned to Stanford in 2014 and is currently a PhD candidate with an interest in VLSI design, 3-D integrated circuits, computer architecture and validation and debug. His current research focuses on addressing challenges in post-silicon validation and debug, specifically aiming to improve bug localization and reduce debug time.